This invention relates to a semiconductor device having a resistive layer of high resistivity and a method of manufacturing the same.
Hitherto, inverter circuits and reference voltage generating circuits, in which a load element consisting of a MOS (metal oxide semicondustor) transistor is connected to a driver MOS transistor, have been used.
However, where a so-called E/D inverter circuit using a MOS transistor as a load element is formed as shown in FIG. 1, the mutual conductance of the MOS transistor is comparatively high, so that an attempt to reduce the mutual conductance for reducing the power consumption of the MOS integrated circuit invites increase of the channel length of the MOS transistor used as load element, which is undesired from the standpoint of achieving high density of integration.
In order to solve this problem, it has been contemplated to form an inverter circuit as shown in FIGS. 2 and 3, wherein a driver MOS transistor comprises source and drain diffusion regions 3 and 4 formed in and contiguous to the principal surface of a semiconductor substrate 2 provided with a field oxide film 1, a gate electron 6 consisting of polycrystalline silicon formed over the exposed surface of the substrate between both the diffusion regions 3 and 4 via a gate oxide film 5 and a lead metal 7 formed to lead from both the diffusion regions 3 and 4, wherein a high resistivity layer 9 of polycrystalline silicon or the like serving as a load resistor element is formed on the field oxide film 1, by separating this layer 9 into high and low resistive sections 9a and 9b after selective thermal impurity diffusion using a mask layer 11 (which may be formed by vapor growing and photoetching a low temperature oxidation film), subsequently forming a protective layer 10 to cover the wafer except for current take-out electrode portions and connecting an electrode portion of the load resistor and the drain diffusion region 4 with a metal lead, thus constructing an inverter circuit as shown in FIG. 4.
This inverter circuit, which is constituted by a semiconductor device having a load resistor consisting of a high resistivity layer, can be extremely reduced in size as compared to one using a MOS transistor as load element. However, even with this circuit sufficiently high density integration cannot be achieved. This is because of the fact that for a given length dimension of the high resistivity section 9a an extra length should be provided for the mask layer 11 for the high resistivity section 9a by taking into considerations the possibility of impurity diffusing into the masked portion (about 10.mu.) at the time of the selective thermal impurity diffusion so that the intended length of its high resistivity is secured.
In addition, the inverter circuit or the like which is produced in the above method is subject to great fluctuations of the resistance of the load resistor.